1. Field of the Invention
The present invention relates to an amplifier circuit, and more particularly to a push-pull-type amplifier circuit employing a stable idling current.
2. Description of the Prior Art
One conventional amplifier circuit of the type will be described below with reference to FIG. 1 of the accompanying drawings.
The push-pull-type amplifier circuit shown in FIG. 1 comprises input terminal IN, power supply terminal 1, first, second, and third transistors M1, M2, M3, reference current supply I.sub.R, and output terminal OUT. It is assumed that the first, second, and third transistors M1, M2, M3 have respective gate-to-source voltages V.sub.GS1, V.sub.GS2, V.sub.GS3, respective drain currents I.sub.D1, I.sub.D2, I.sub.D3, respective transistor gain coefficients .beta..sub.1, .beta..sub.2, .beta..sub.3, and a threshold voltage V.sub.T, and that a power supply voltage V.sub.DD is applied to power supply terminal 1 and a current i.sub.R flows through reference current supply I.sub.R. An idling current I.sub.0, which flows when I.sub.D2 =I.sub.D3, is determined according to the following equations: ##EQU1##
The conventional push-pull-type amplifier circuit outputs an idling current I.sub.0 depending on the power supply voltage V.sub.DD that is applied to power supply terminal 1. For example, if V.sub.T =0.7 V and V.sub.GS1 =2.5 V, the idling current I.sub.0 when V.sub.DD =5.5 V and 4.5 V is given as follows:
(1) When V.sub.DD =4.5 V, if V.sub.GS2 =V.sub.GS3 =V.sub.GS, then V.sub.GS =1.0 (V) from the equation (4). If .beta..sub.2 =.beta..sub.3 =.beta., then from the equations (1), (2), (3), I.sub.0 =I.sub.D2 =I.sub.D3 =(1/2).multidot..beta..multidot.(V.sub.GS -V.sub.T).sup.2 =(1/2).multidot..beta..multidot.(1.0-0.7).sup.2 =(1/2).multidot..beta..times.0.09. PA1 (2) When V.sub.DD =5.5 V, V.sub.GS2 +V.sub.GS3 =V.sub.DD -V.sub.GS1 =5.5-2.5=3.0 (V) from the equation (4). If V.sub.GS2 =V.sub.GS3 =V.sub.GS, then V.sub.GS =1.5 (V). If .beta..sub.2 =.beta..sub.3 =.beta., then from the equations (1), (2), (5), I.sub.0 =I.sub.D2 =I.sub.D3 =(1/2).multidot..beta..multidot.(V.sub.GS -V.sub.T).sup.2 =(1/2).multidot..beta..multidot.(1.5-0.7).sup.2 =(1/2).multidot..beta..times.0.64.
From (1) and (2) above, EQU I.sub.0 (V.sub.DD =4.5 V):I.sub.0 (V.sub.DD =5.5 V)=1.0:7.1.
The mutual conductance gm (=.sqroot.2.beta.I.sub.0) of the output transistor when V.sub.DD =5.5 V greatly differs from that when V.sub.DD =4.5 V.
When a load capacitor C.sub.L (not shown) is connected to output terminal OUT, the gain bandwidth (GB product) of the amplifier circuit is expressed as follows: EQU GB=gm/2.pi.C.sub.L.
If the amplifier circuit is used as the output stage circuit of a well-known two-stage operational amplifier composed of a differential stage circuit and an output stage circuit, then since the bandwidth of the output stage circuit greatly varies depending on the power supply voltage V.sub.DD, the operational amplifier has poor stability and tends to oscillate easily.